超前进位加法器

• 超前进位加法器(carry lookahead adder, CLA)，该加法器改进了行波进位加法器的关键路径，通过并行计算进位的方式解决了行波进位加法器的进位依赖问题，其进位输入是通过前面全加器的输入经逻辑运算而得。
• CLA位数大于4时，超前进位逻辑会变得异常复杂、单元面积耗费大。于是对于大于4位的CLA使用，常将4位CLA进行级联实现，或者组间超前进位的方式实现，即进行多级超前进位。

//4位CLA实现
module  operator_A(
input   A,
input   B,
output  P,
output  G
);

assign  P=A^B;
assign  G=A&B;

endmodule

module  operator_B(
input   P,G,P1,G1,
output  Po,Go
);

assign  Po=P&P1;
assign  Go=G|(P&G1);

endmodule

module  operator_C(
input   P,G,G1,
output  Go
);

assign  Go=G|(P&G1);

endmodule

module CLA_4bit(
    input [3:0] i_a,
    input [3:0] i_b,
    input i_c,
    output [3:0] o_s,
    output o_c,
    output o_p, 
    output o_g
    );

    wire [3:0] P0, G0;
    operator_A operator_A_0(i_a[0], i_b[0], P0[0], G0[0]);
    operator_A operator_A_1(i_a[1], i_b[1], P0[1], G0[1]);
    operator_A operator_A_2(i_a[2], i_b[2], P0[2], G0[2]);
    operator_A operator_A_3(i_a[3], i_b[3], P0[3], G0[3]);

    wire [3:0] C;
    wire P1, G1;
    wire P2, G2;
    wire P3, G3;

    operator_C operator_C_0(P0[0], G0[0], i_c, C[0]);

    operator_B operator_B_0(P0[1], G0[1], P0[0], G0[0], P1, G1);
    operator_C operator_C_1(P1, G1, i_c, C[1]);

    operator_B operator_B_1(P0[2], G0[2], P1, G1, P2, G2);
    operator_C operator_C_2(P2, G2, i_c, C[2]);

    operator_B operator_B_2(P0[3], G0[3], P2, G2, P3, G3);
    operator_C operator_C_3(P3, G3, i_c, C[3]);

    assign o_s[0] = P0[0] ^ i_c;
    assign o_s[1] = P0[1] ^ C[0];
    assign o_s[2] = P0[2] ^ C[1];
    assign o_s[3] = P0[3] ^ C[2];
    assign o_c = C[3];
    assign o_p = P3;
    assign o_g = G3;

endmodule

//16位CLA实现
module  operator_A(
input   A,
input   B,
output  P,
output  G
);

assign  P=A^B;
assign  G=A&B;

endmodule

module  operator_B(
input   P,G,P1,G1,
output  Po,Go
);

assign  Po=P&P1;
assign  Go=G|(P&G1);

endmodule

module  operator_C(
input   P,G,G1,
output  Go
);

assign  Go=G|(P&G1);

endmodule

module CLA_4bit(
    input [3:0] i_a,
    input [3:0] i_b,
    input i_c,
    output [3:0] o_s,
    output o_c,
    output o_p, 
    output o_g
    );

    wire [3:0] P0, G0;
    operator_A operator_A_0(i_a[0], i_b[0], P0[0], G0[0]);
    operator_A operator_A_1(i_a[1], i_b[1], P0[1], G0[1]);
    operator_A operator_A_2(i_a[2], i_b[2], P0[2], G0[2]);
    operator_A operator_A_3(i_a[3], i_b[3], P0[3], G0[3]);

    wire [3:0] C;
    wire [3:1] P1, G1;

    operator_C operator_C_0(P0[0], G0[0], i_c, C[0]);

    operator_B operator_B_0(P0[1], G0[1], P0[0], G0[0], P1[1], G1[1]);
    operator_C operator_C_1(P1[1], G1[1], i_c, C[1]);

    operator_B operator_B_1(P0[2], G0[2], P1[1], G1[1], P1[2], G1[2]);
    operator_C operator_C_2(P1[2], G1[2], i_c, C[2]);

    operator_B operator_B_2(P0[3], G0[3], P1[2], G1[2], P1[3], G1[3]);
    operator_C operator_C_3(P1[3], G1[3], i_c, C[3]);

    assign o_s[0] = P0[0] ^ i_c;
    assign o_s[1] = P0[1] ^ C[0];
    assign o_s[2] = P0[2] ^ C[1];
    assign o_s[3] = P0[3] ^ C[2];
    assign o_c = C[3];
    assign o_p = P1[3];
    assign o_g = G1[3];

endmodule

module LAC(
    input [3:0] P1,
    input [3:0] G1,
    input i_c,
    output [3:0] C,
    output o_p,
    output o_g
);

    wire [3:1] P2, G2;
    operator_C operator_C_0(P1[0], G1[0], i_c, C[0]);

    operator_B operator_B_0(P1[1], G1[1], P1[0], G1[0], P2[1], G2[1]); 
    operator_C operator_C_1(P2[1], G2[1], i_c, C[1]);

    operator_B operator_B_1(P1[2], G1[2], P2[1], G2[1], P2[2], G2[2]);
    operator_C operator_C_2(P2[2], G2[2], i_c, C[2]);

    operator_B operator_B_2(P1[3], G1[3], P2[2], G2[2], P2[3], G2[3]);
    operator_C operator_C_3(P2[3], G2[3], i_c, C[3]);

    assign o_p = P2[3];
    assign o_g = G2[3];

endmodule

module CLA_16bit(
    input [15:0] i_a,
    input [15:0] i_b,
    input i_c,
    output [15:0] o_s,
    output o_c,
    output o_p,
    output o_g
);

    wire [3:0] P, G;
    wire [3:0] C;

    CLA_4bit CLA_4bit_0(
        .i_a    (i_a[3:0]),
        .i_b    (i_b[3:0]),
        .i_c    (i_c),
        .o_s    (o_s[3:0]),
        .o_c    (),
        .o_p    (P[0]),
        .o_g    (G[0])
    );

    CLA_4bit CLA_4bit_1(
        .i_a    (i_a[7:4]),
        .i_b    (i_b[7:4]),
        .i_c    (C[0]),
        .o_s    (o_s[7:4]),
        .o_c    (),
        .o_p    (P[1]),
        .o_g    (G[1])
    );

    CLA_4bit CLA_4bit_2(
        .i_a    (i_a[11:8]),
        .i_b    (i_b[11:8]),
        .i_c    (C[1]),
        .o_s    (o_s[11:8]),
        .o_c    (),
        .o_p    (P[2]),
        .o_g    (G[2])
    );

    CLA_4bit CLA_4bit_3(
        .i_a    (i_a[15:12]),
        .i_b    (i_b[15:12]),
        .i_c    (C[2]),
        .o_s    (o_s[15:12]),
        .o_c    (),
        .o_p    (P[3]),
        .o_g    (G[3])
    );

    assign o_c = C[3];

    LAC LAC_4x4(
        .P1     (P),
        .G1     (G),
        .i_c    (i_c),
        .C      (C),
        .o_p    (o_p),
        .o_g    (o_g)
    );

endmodule

CLA相应逻辑推导如下：