行波进位加法器

• 行波进位加法器(ripple carry adder, RCA)，该加法器简单由N位1bit全加器串联而成。每个全加器的cout为下一个的cin，故称ripple carry adder。
• 缺点在于超长的串行进位链严重限制加法器的运算速度

接口定义如下：

ripple_carry_addr RCA(
    input   [width-1 : 0] i_a,
    input   [width-1 : 0] i_b,
    input   i_c,
    output  [width-1 : 0] o_s,
    output  o_c
);

//4位RCA实现
module  operator_A(
    input   i_a,
    input   i_b,
    input   i_c,
    output  o_s,
    output  o_c
);

assign o_s = i_a ^ i_b ^ i_c;
//assign o_c = (i_a & i_b) | (i_c & (i_a | i_b));
assign o_c = (i_a & i_b) | (i_c & (i_a ^ i_b));

endmodule

module RCA_4bit(
    input [3:0] i_a,
    input [3:0] i_b,
    input i_c,
    output [3:0] o_s,
    output o_c
    );

    wire [3:0] P0, G0;
    operator_A operator_A_0(i_a[0], i_b[0], i_c, P0[0], G0[0]);
    operator_A operator_A_1(i_a[1], i_b[1], G0[0], P0[1], G0[1]);
    operator_A operator_A_2(i_a[2], i_b[2], G0[1], P0[2], G0[2]);
    operator_A operator_A_3(i_a[3], i_b[3], G0[2], P0[3], G0[3]);

    assign o_s[0] = P0[0];
    assign o_s[1] = P0[1];    
    assign o_s[2] = P0[2];
    assign o_s[3] = P0[3];
    assign o_c = G0[3];

endmodule

//16位RCA实现
module  operator_A(
    input   i_a,
    input   i_b,
    input   i_c,
    output  o_s,
    output  o_c
);

assign o_s = i_a ^ i_b ^ i_c;
//assign o_c = (i_a & i_b) | (i_c & (i_a | i_b));
assign o_c = (i_a & i_b) | (i_c & (i_a ^ i_b));

endmodule

module RCA_16bit(
    input [15:0] i_a,
    input [15:0] i_b,
    input i_c,
    output [15:0] o_s,
    output o_c
    );

    wire [15:0] P0, G0;
    operator_A operator_A_0(i_a[0], i_b[0], i_c, P0[0], G0[0]);
    operator_A operator_A_1(i_a[1], i_b[1], G0[0], P0[1], G0[1]);
    operator_A operator_A_2(i_a[2], i_b[2], G0[1], P0[2], G0[2]);
    operator_A operator_A_3(i_a[3], i_b[3], G0[2], P0[3], G0[3]);
    operator_A operator_A_4(i_a[4], i_b[4], G0[3], P0[4], G0[4]);
    operator_A operator_A_5(i_a[5], i_b[5], G0[4], P0[5], G0[5]);
    operator_A operator_A_6(i_a[6], i_b[6], G0[5], P0[6], G0[6]);
    operator_A operator_A_7(i_a[7], i_b[7], G0[6], P0[7], G0[7]);
    operator_A operator_A_8(i_a[8], i_b[8], G0[7], P0[8], G0[8]);
    operator_A operator_A_9(i_a[9], i_b[9], G0[8], P0[9], G0[9]);
    operator_A operator_A_10(i_a[10], i_b[10], G0[9], P0[10], G0[10]);
    operator_A operator_A_11(i_a[11], i_b[11], G0[10], P0[11], G0[11]);
    operator_A operator_A_12(i_a[12], i_b[12], G0[11], P0[12], G0[12]);
    operator_A operator_A_13(i_a[13], i_b[13], G0[12], P0[13], G0[13]);
    operator_A operator_A_14(i_a[14], i_b[14], G0[13], P0[14], G0[14]);
    operator_A operator_A_15(i_a[15], i_b[15], G0[14], P0[15], G0[15]);

    assign o_s[0] = P0[0];
    assign o_s[1] = P0[1];    
    assign o_s[2] = P0[2];
    assign o_s[3] = P0[3];
    assign o_s[4] = P0[4];
    assign o_s[5] = P0[5];
    assign o_s[6] = P0[6];
    assign o_s[7] = P0[7];
    assign o_s[8] = P0[8];
    assign o_s[9] = P0[9];
    assign o_s[10] = P0[10];
    assign o_s[11] = P0[11];
    assign o_s[12] = P0[12];
    assign o_s[13] = P0[13];
    assign o_s[14] = P0[14];
    assign o_s[15] = P0[15];
    assign o_c = G0[15]; 

endmodule

4位RCA的逻辑图如下